M48T201Y datasheet(15/37 Pages) STMICROELECTRONICS

15 / 37 page

M48T201Y, M48T201V

Operation

15/37

Table 4.

Write mode AC characteristics

2.4

Data retention mode

With valid VCC applied, the M48T201Y/V can be accessed as described above with READ

or WRITE cycles. Should the supply voltage decay, the M48T201Y/V will automatically

deselect, write protecting itself (and any external SRAM) when VCC falls between VPFD

(max) and VPFD (min). This is accomplished by internally inhibiting access to the clock

registers via the E signal. At this time, the reset pin (RST) is driven active and will remain

active until VCC returns to nominal levels. External RAM access is inhibited in a similar

manner by forcing ECON to a high level. This level is within 0.2 V of the VBAT. ECON will

remain at this level as long as VCC remains at an out-of-tolerance condition. When VCC falls

below the level of the battery (VBAT), power input is switched from the VCC pin to the

SNAPHAT® battery and the clock registers are maintained from the attached battery supply.

External RAM is also powered by the SNAPHAT battery. All outputs except GCON, ECON,

RST, IRQ/FT and VOUT, become high impedance. The VOUT pin is capable of supplying

100 µA of current to the attached memory with less than 0.3 V drop under this condition. On

power up, when VCC returns to a nominal value, write protection continues for 200 ms (max)

by inhibiting ECON. The RST signal also remains active during this time (see Figure 14 on

page 30).

Symbol

Parameter(1)

Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where

noted).

M48T201Y

M48T201V

Unit

–70

–85

Min

Max

Min

Max

tAVAV

WRITE cycle time

tAVWL

Address valid to WRITE enable low

tAVEL

Address valid to chip enable low

tWLWH

WRITE enable pulse width

tELEH

Chip enable low to chip enable high

tWHAX

WRITE enable high to address transition

tEHAX

Chip enable high to address transition

tDVWH

Input valid to WRITE enable high

tDVEH

Input valid to chip enable high

tWHDX

WRITE enable high to input transition

tEHDX

Chip enable high to input transition

tWLQZ

(2)(3)

CL = 5 pF

If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

WRITE enable low to output High-Z

tAVWH

Address valid to WRITE enable high

tAVEH

Address valid to chip enable high

tWHQX

(2)(3)

WRITE enable high to output transition

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