M48T201Y datasheet(13/37 Pages) STMICROELECTRONICS

13 / 37 page

M48T201Y, M48T201V

Operation

13/37

Table 3.

Read mode AC characteristics

2.3

Write mode

The M48T201Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable)

are low state after the address inputs are stable. The start of a WRITE is referenced from

the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge

of W or E. The addresses must be held valid throughout the cycle. E or W must return high

for a minimum of tEHAX from chip enable or tWHAX from WRITE enable prior to the initiation

of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE

and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid

bus contention; although, if the output bus has been activated by a low on E and G a low on

W will disable the outputs tWLQZ after W falls.

When the address value presented to the M48T201Y/V during the WRITE is in the range of

7FFFFh-7FFF0h, one of the on-board TIMEKEEPER® registers will be selected and data

will be written into the device. When the address value presented to M48T201Y/V is outside

the range of TIMEKEEPER registers, an external SRAM location is selected.

Symbol

Parameter(1)

Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where

noted).

M48T201Y

M48T201V

Unit

–70

–85

Min

Max

Min

Max

tAVAV

READ cycle time

tAVQV

Address valid to output valid

tELQV

Chip enable low to output valid

tGLQV

Output enable low to output valid

tELQX

(2)

CL = 5 pF.

Chip enable low to output transition

tGLQX

(2)

Output enable low to output transition

tEHQZ

(2)

Chip enable high to output Hi-Z

tGHQZ

(2)

Output enable high to output Hi-Z

tAXQX

Address transition to output transition

tAOEL

External SRAM address to GCON low

tAOEH

Supervisor SRAM address to GCON high

tEPD

E to ECON low or high

tOERL

G low to GCON low

tRO

G high to GCON high

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