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HT68FU50 数据表(PDF) 121 Page - Holtek Semiconductor Inc |
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HT68FU50 数据表(HTML) 121 Page - Holtek Semiconductor Inc |
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121 / 244 page  HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Rev. 1.50 121 March 15, 2011 ¨ TM1BL Register - 10-bit ETM Bit 76543210 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 00000000 Bit7~0 TM1BL: TM1 CCRB Low Byte Register bit 7~bit 0 TM1 10-bit CCRB bit 7~bit 0 ¨ TM1BH Register - 10-bit ETM Bit 76543210 Name ¾¾¾¾¾¾ D9 D8 R/W ¾¾¾¾¾¾ R/W R/W POR ¾¾¾¾¾¾ 00 Bit 7~2 Unimplemented, read as ²0² Bit 1~0 TM1BH: TM1 CCRB High Byte Register bit 1~bit 0 TM1 10-bit CCRB bit 9 ~ bit 8 Enhanced Type TM Operating Modes The Enhanced Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnAM1 and TnAM0 bits in the TMnC1, and the TnBM1 and TnBM0 bits in the TMnC2 register. ETM Operating Mode CCRA Com- pare Match Output Mode CCRA Timer/Coun- ter Mode CCRA PWM Output Mode CCRA Single Pulse Output Mode CCRA Input Capture Mode CCRB Compare Match Output Mode Ö ¾¾¾¾ CCRB Timer/Counter Mode ¾ Ö ¾¾¾ CCRB PWM Output Mode ¾ ¾Ö¾ ¾ CCRB Single Pulse Output Mode ¾ ¾ ¾Ö¾ CCRB Input Capture Mode ¾¾¾¾ Ö ²Ö²: permitted; ²¾² : not permitted Compare Output Mode To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1/TMnC2 registers should be all cleared to zero. In this mode once the counter is en- abled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a com- pare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt re- quest flags for Comparator A and Comparator P respec- tively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF inter- rupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt re- quest flag will be generated. |
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