HT68FU50 datasheet(122/244 Pages) HOLTEK

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.50

122

March 15, 2011

As the name of the mode suggests, after a comparison

is made, the TM output pin, will change state. The TM

output pin condition however only changes state when

an TnAF or TnBF interrupt request flag is generated af-

ter a compare match occurs from Comparator A or Com-

parator B. The TnPF interrupt request flag, generated

from a compare match from Comparator P, will have no

effect on the TM output pin. The way in which the TM

output pin changes state is determined by the condition

of the TnAIO1 and TnAIO0 bits in the TMnC1 register for

ETM CCRA, and the TnBIO1 and TnBIO0 bits in the

TMnC2 register for ETM CCRB. The TM output pin can

be selected using the TnAIO1, TnAIO0 bits (for the

TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB_0,

TPnB_1 or TPnB_2 pins) to go high, to go low or to tog-

gle from its present condition when a compare match

occurs from Comparator A or a compare match occurs

from Comparator B. The initial condition of the TM out-

put pin, which is setup after the TnON bit changes from

low to high, is setup using the TnAOC or TnBOC bit for

TPnA or TPnB_0, TPnB_1, TPnB_2 output pins. Note

that if the TnAIO1,TnAIO0 and TnBIO1, TnBIO0 bits are

zero then no pin change will take place.

Counter Value

0x3FF

CCRP

CCRA

TnON

TnPAU

TnAPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TPnA O/P

Time

CCRP=0

CCRP > 0

Counter overflow

CCRP > 0

Counter cleared by CCRP value

Pause

Resume

Stop

Counter

Restart

TnCCLR = 0; TnAM [1:0] = 00

Output pin set to

initial Level Low

if TnAOC=0

Output Toggle with

TnAF flag

Note TnAIO [1:0] = 10

Active High Output select

Here TnAIO [1:0] = 11

Toggle Output select

Output not affected by TnAF

flag. Remains High until reset

by TnON bit

Output Pin

Reset to Initial value

Output controlled by

other pin-shared function

Output Inverts

when TnAPOL is high

ETM CCRA Compare Match Output Mode -- TnCCLR = 0

Note:

1. With TnCCLR=0, a Comparator P match will clear the counter

2. The TPnA output pin is controlled only by the TnAF flag

3. The output pin is reset to its initial state by a TnON bit rising edge

HT68FU50 数据表(PDF) 122 Page - Holtek Semiconductor Inc

HT68FU50 数据表(HTML) 122 Page - Holtek Semiconductor Inc

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