HT68FU50 datasheet(127/244 Pages) HOLTEK

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.50

127

March 15, 2011

· ETM, PWM Mode, Center-aligned Mode, TnCCLR=1

CCRA

511

512

1021

1022

1023

Period

1022

1024

2042

2044

2046

B Duty

(CCRB

´2)-1

Counter Value

CCRP

CCRA

TnON

TnPAU

TnAPOL

CCRA Int.

Flag TnAF

CCRB Int.

Flag TnBF

TPnA Pin

(TnAOC=1)

Time

Counter Cleared by CCRP

Pause

Resume

Stop

Counter

Restart

TnCCLR = 0;

TnAM [1:0] = 10, TnBM [1:0] = 10;

TnPWM [1:0] = 00

Output Pin

Reset to Initial value

Output controlled by

other pin-shared function

Output Inverts

when TnAPOL

is high

CCRB

CCRP Int.

Flag TnPF

TPnB Pin

(TnBOC=1)

TPnB Pin

(TnBOC=0)

Duty Cycle

set by CCRA

Duty Cycle

set by CCRB

PWM Period set by CCRP

Duty Cycle

set by CCRA

Duty Cycle

set by CCRA

PWM Mode -- Edge Aligned

Note:

1. Here TnCCLR=0 therefore CCRP clears the counter and determines the PWM period

2. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0]) = 00 or 01

3. CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty

HT68FU50 数据表(PDF) 127 Page - Holtek Semiconductor Inc

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HT68FU50 数据表(PDF) 127 Page - Holtek Semiconductor Inc

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