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HT68FU50 数据表(PDF) 128 Page - Holtek Semiconductor Inc |
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HT68FU50 数据表(HTML) 128 Page - Holtek Semiconductor Inc |
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128 / 244 page  HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Rev. 1.50 128 March 15, 2011 Counter Value CCRA TnON TnPAU TnBPOL CCRB Int. Flag TnBF Time Counter Cleared by CCRA Pause Resume Stop Counter Restart TnCCLR = 1; TnBM [1:0] = 10; TnPWM [1:0] = 00 Output Pin Reset to Initial value Output controlled by other pin-shared function Output Inverts when TnBPOL is high CCRB CCRP Int. Flag TnPF TPnB Pin (TnBOC=1) TPnB Pin (TnBOC=0) Duty Cycle set by CCRB PWM Period set by CCRA ETM PWM Mode -- Edge Aligned Note: 1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period 2. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01 3. The CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 4. Here the TM pin control register should not enable the TPnA pin as a TM output pin. |
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