HT68FU50 datasheet(185/244 Pages) HOLTEK

185 / 244 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.50

185

March 15, 2011

For read operations, the device will begin to execute the

command only after it receives an 8-bit read command

after which it will be ready to output data. If necessary,

the master can de-assert the SCS pin to abort the trans-

action at any time which will cause any data transac-

tions to be abandoned.

UART Module External Pin Interfacing

To communicate with an external serial interface, the in-

ternal UART has two external pins known as TX and RX.

The TX pin is the UART transmitter serial data output pin

if the corresponding control bits named UARTEN in

UCR1 register and TXEN in UCR2 register are set to 1.

If the control bit UARTEN or TXEN is equal to zero, the

TX pin is in the state of high impedance. Similarly, the

RX pin is the UART receiver serial data input pin if the

corresponding control bits named UARTEN and RXEN

in UCR1 and UCR2 registers are set to 1. If the control

bit UARTEN or RXEN is equal to zero, the RX pin is in

the state of high impedance.

UART Data Transfer Scheme

The following block diagram shows the overall data

transfer structure arrangement for the UART. The actual

data to be transmitted from the MCU is first transferred

to the TXR register by the application program. The data

will then be transferred to the Transmitter Shift Register

named TSR from where it will be shifted out, LSB first,

onto the TX pin at a rate controlled by the Baud Rate

Generator. Only the TXR register is accessible to the

application program, the Transmitter Shift Register is

not mapped into the Data Memory area and is inacces-

sible to the application program.

Data to be received by the UART is accepted on the ex-

ternal RX pin, from where it is shifted in, LSB first, to the

Receiver Shift Register named RSR at a rate controlled

by the Baud Rate Generator. When the shift register is

full, the data will then be transferred from the shift regis-

ter to the internal RXR register, where it is buffered and

can be manipulated by the application program. Only

the RXR register is accessible to the application pro-

gram, the Receiver Shift Register is not mapped into the

Data Memory area and is inaccessible to the application

program. It should be noted that the actual register for

data transmission and reception, although referred to in

the text, and in application programs, as separate TXR

and RXR registers, only exists as a single shared regis-

ter physically. This shared register known as the

TXR/RXR register is used for both data transmission

and data reception.

SDO

SDI

SCK

SCS

Writing Type Format: 8-bit Command Input + 8-bit Data Input

SDO

SDI

SCK

SCS

Reading Type Format: 8-bit Command Input + 8-bit Data Output

MSB

LSB

Transmitter Shift Register (TSR)

MSB

LSB

Receiver Shift Register (RSR)

TX Pin

RX Pin

Baud Rate

Generator

TX Register (TXR)

RX Register (RXR)

Buffer 1

Buffer 2

Buffer 3

Data to be transmitted

Data received

UART Data Transfer Scheme

HT68FU50 数据表(PDF) 185 Page - Holtek Semiconductor Inc

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