IMX28CEC datasheet(35/70 Pages) FREESCALE

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i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1

Freescale Semiconductor

3.5.4.1

ENET MII Mode Timing

This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal

timings.

3.5.4.1.1

MII Receive Signal Timing (ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER,

and ENET0_RX_CLK)

The receiver functions correctly up to an ENET0_RX_CLK maximum frequency of 25 MHz + 1%. There

is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the

ENET0_RX_CLK frequency.

Figure 9 shows MII receive signal timings. Table 39 describes the timing parameters (M1–M4) shown in

the figure.

Figure 9. MII Receive Signal Timing Diagram

1 ENET0_RX_DV, ENET0_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

3.5.4.1.2

MII Transmit Signal Timing (ENET0_TXD[3:0], ENET0_TX_EN,

ENET0_TX_ER, and ENET0_TX_CLK)

The transmitter functions correctly up to an ENET0_TX_CLK maximum frequency of 25 MHz + 1%.

There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed

twice the ENET0_TX_CLK frequency.

Table 39. MII Receive Signal Timing

Characteristic1

Min.

Max.

Unit

ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER to

ENET0_RX_CLK setup

5—

ENET0_RX_CLK to ENET0_RXD[3:0], ENET0_RX_DV,

ENET0_RX_ER hold

5—

ENET0_RX_CLK pulse width high

35%

65%

ENET0_RX_CLK

period

ENET0_RX_CLK pulse width low

35%

65%

ENET0_RX_CLK

period

ENET0_RX_CLK (input)

ENET0_RXD[3:0] (inputs)

ENET0_RX_DV

ENET0_RX_ER

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