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IMX28CEC 数据表(PDF) 59 Page - Freescale Semiconductor, Inc

部件名 IMX28CEC
功能描述  Processors Data Sheet for Consumer Products
PDF  70 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

IMX28CEC 数据表(HTML) 59 Page - Freescale Semiconductor, Inc

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i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
59
3.5.15
UART (UARTAPP and DebugUART) AC Timing
This section describes the UART module AC timing which is applicable to both UARTAPP and
DebugUART.
3.5.15.1
UART Transmit Timing
Figure 39 shows the UART transmit timing, showing only eight data bits and one stop bit. Table 63
describes the timing parameter (UA1) shown in the figure.
Figure 42. UART Transmit Timing Diagram
3.5.15.2
UART Receive Timing
Figure 43 shows the UART receive timing, showing only eight data bits and one stop bit. Table 64
describes the timing parameter (UA2) shown in the figure.
Figure 43. UART Receive Timing Diagram
Table 63. UART Transmit Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
UA1
Transmit Bit Time
tTbit
1/Fbaud_rate
1 – T
ref_clk
2
1 F
baud_rate: Baud rate frequency. The maximum baud rate the UARTAPP can support is 3.25 Mbps. The maximum baud rate of
DebugUART is 115.2 kbps.
2 T
ref_clk: The period of UART reference clock ref_clk (which is APBX clock = 24 MHz).
1/Fbaud_rate + Tref_clk
Bit 1
Bit 2
Bit 0
Bit 4
Bit 5
Bit 6
Bit 7
TXD
(output)
Bit 3
Start
Bit
STOP
BIT
Next
Start
Bit
Possible
Parity
Bit
Par Bit
UA1
UA1
UA1
UA1
Bit 1
Bit 2
Bit 0
Bit 4
Bit 5
Bit 6
Bit 7
RXD
(input)
Bit 3
Start
Bit
STOP
BIT
Next
Start
Bit
Possible
Parity
Bit
Par Bit
UA2
UA2
UA2
UA2



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