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IMX28CEC 数据表(PDF) 16 Page - Freescale Semiconductor, Inc

部件名 IMX28CEC
功能描述  Processors Data Sheet for Consumer Products
PDF  70 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

IMX28CEC 数据表(HTML) 16 Page - Freescale Semiconductor, Inc

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i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
16
Freescale Semiconductor
3.1.2.1
Recommended Operating Conditions for Specific Clock Targets
Table 14 through Table 18 provide the recommended operating conditions for specific clock targets.
7 Untuned.
Table 14. System Clocks
Name
Min. Freq. (MHz)
Max. Freq. (MHz)
Description
clk_gpmi
—
TBD
General purpose memory interface clock domain
clk_ssp
—
TBD
SSP interface clock domain
Table 15. Recommended Operating States—289-Pin BGA Package
VDDD
(V)
VDDD
Brown-out
(V)
HW_
DIGCTRL
ARMCACH
E1
1 All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.
CPUCLK
/ clk_p
Frequency
(MHz)
HW_
CLKCTRL
CPU_DIV_CP
U
HW_
CLKCTRL
FRAC_
CPUFRC
/ PFD
AHBCLK
/ clk_h
Frequency
(MHz)
HW_
CLKCTRL
HBUS_DI
V
EMICLK
/ clk_emi
Frequency
(MHz)
HW_
CLKCTRL
EMI_
DIV_EMI
HW_
CLKCTRL
FRAC_
EMIFRAC
Supported
DRAM
TBD
TBD
00
64
5
27
64
1
130.91
2
33
DDR2
mDDR
1.350
1.250
00
261.81
1
33
130.91
2
130.91
2
33
DDR2
mDDR
1.350
1.250
00
360
1
24
120.00
3
130.91
2
33
DDR2
mDDR
1.450
1.350
00
392.72
1
22
130.91
3
160.00
2
27
DDR2
mDDR
1.550
1.450
00
454.73
1
19
151.57
3
205.71
2
21
DDR2
mDDR
Table 16. Recommended Operating Conditions—CPU Clock (clk_p)
Minimum
VDDD (V)
Minimum
VDDDBrown-out (V)
HW_DIGCTRL
ARMCACHE1
1 All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.
HW_CLKCTRL
FRAC_CPUFRC / PFD
CPUCLK / clk_p
Frequency max (MHz)
TBD
TBD
00
27 - 35
TBD
1.350
1.250
00
18 - 35
360
1.450
1.350
00
18 - 35
392.72
1.550
1.450
00
18 - 35
454.73



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