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数据搜索系统，热门电子元器件搜索 |
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IMX28CEC 数据表(PDF) 52 Page - Freescale Semiconductor, Inc |
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IMX28CEC 数据表(HTML) 52 Page - Freescale Semiconductor, Inc |
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52 / 70 page  i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 52 Freescale Semiconductor 3.5.12.1.5 SAIF Receiver Timing Figure 34 shows the timing for the SAIF receiver with internal clock. Table 56 describes the timing parameters (SS1–SS17) shown in the figure. Figure 34. SAIF Receiver Timing Diagram Table 55. SAIF Transmitter Timing ID Parameter Min. Max. Unit SS1 BITCLK period 81.4 — ns SS2 BITCLK high period 36.0 — ns SS3 BITCLK rise time — 6.0 ns SS4 BITCLK low period 36.0 — ns SS5 BITCLK fall time — 6.0 ns SS6 BITCLK high to LRCLK high — 15.0 ns SS7 BITCLK high to LRCLK low — 15.0 ns SS8 LRCLK rise time — 6.0 ns SS9 LRCLK fall time — 6.0 ns SS10 BITCLK high to SDATA valid from high impedance — 15.0 ns SS11 BITCLK high to SDATA high/low — 15.0 ns SS12 BITCLK high to SDATA high impedance — 15.0 ns SS13 SDATA rise/fall time — 6.0 ns BITCLK LRCLK SDATA0-2 SS1 SS4 SS2 SS16 SS17 SS14 SS15 SS3 SS5 |
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