AS3421 datasheet(22/61 Pages) AMSCO

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AS3421 AS3422

Datasheet - D e t a i l e d D e s c r i p t i o n

The OTP memory can be accessed in the following ways:

LOAD Operation. The LOAD operation reads the OTP fuses and loads the contents into the OTP register. A LOAD operation is automatically

executed after each power-on-reset.

WRITE Operation. The WRITE operation allows a temporary modification of the OTP register. It does not program the OTP. This operation

can be invoked multiple times and will remain set while the chip is supplied with power and while the OTP register is not modified with another

WRITE or LOAD operation.

READ Operation. The READ operation reads the contents of the OTP register, for example to verify a WRITE command or to read the OTP

memory after a LOAD command.

BURN Operation. The BURN operation programs the contents of the OTP register permanently into the OTP fuses. Don’t use old or nearly

empty batteries for burning the fuses.

Attention: If you once burn the OTP_LOCK bit, no further programming, e.g. setting additional “0” to “1”, of the OTP can be done.

For production, the OTP_LOCK bit must be set to avoid an unwanted change of the OTP content during the lifetime of the product.

9.7.2

OTP Fuse Burning

As many wireless applications like Bluetooth single chip solutions support programmable solutions as well as ROM versions it is in ROM

versions necessary to store microphone gain compensation data and the general ANC configuration inside the ANC chip because there is not

other way to configure the ANC chip during startup. In order to guaranty successful trimming of AS3421/22 it is necessary to provide a decent

environment for the trimming process. In Figure 26 a principal block diagram is shown for trimming the AS3421/22 properly in production.

Figure 26. Block Diagram for Production Environment

The most

important block is the external power supply. Usually it is possible to trim the AS3421/22 with a single supply voltage of min. 1.7V in

laboratory environment but as soon as it comes to mass production we highly recommend buffering also VNEG supply of the chip. As highlighted

in the block diagram it is mandatory to get a voltage difference between VPOS and VNEG of min. 3.4V to guaranty proper trimming of the device.

no current sink capability, therefore it is possible to buffer it external with a negative power supply. The VNEG

voltage applied to VNEG pin must be

lower than the voltage created with the charge pump. This means if the typical VNEG output voltage is -1.5V you can easily apply externally -

1.7V. The charge pump switches then automatically into skip mode.

Important for applying an external buffer and switching on the ANC device is the timing in order to avoid latch up on the ANC device. The timing

diagram in Figure 2 shows clearly that it is important that there is a certain delay between VBAT and

the MODE /CSCL pin necessary. This delay is

mandatory in order to guaranty that the device starts up properly. In case AS350x is used the delay between VBAT and MODE/CSCL is not

necessary. The MODE /CSCL pin powers the ANC device up and the whole sequence to power up the internal charge pump of AS34x0 and

AS350x takes approximately 1ms. Once VNEG is settled the external VNEG buffer (e.g. power supply) can be enabled in order to support the

charge pump especially during the trim process which can now be started.

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