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AS3421 数据表(PDF) 27 Page - ams AG |
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AS3421 数据表(HTML) 27 Page - ams AG |
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27 / 61 page ![]() www.austriamicrosystems.com Revision 0.90 27 - 61 AS3421 AS3422 Datasheet - D e t a i l e d D e s c r i p t i o n 9.8.2 Parameter Figure 34. 2-Wire Serial Timing VBAT >=1.4V 1 , TA=25ºC, unless otherwise specified. Table 14. 2-Wire Serial Parameter Symbol Parameter Condition Min Typ Max Unit VCSL CSCL, CSDA Low Input Level (max 30%VBAT) 0 - 0.42 V VCSH CSCL, CSDA High Input Level CSCL, CSDA (min 70%VBAT) 0.98 - V HYST CSCL, CSDA Input Hysteresis 200 450 800 mV VOL CSDA Low Output Level at 3mA - - 0.4 V Tsp Spike insensitivity 50 100 - ns TH Clock high time max. 400kHz clock speed 500 ns TL Clock low time max. 400kHz clock speed 500 ns TSU CSDA has to change Tsetup before rising edge of CSCL 250 - - ns THD No hold time needed for CSDA relative to rising edge of CSCL 0 - - ns TS CSDA H hold time relative to CSDA edge for start/stop/rep_start 200 - - ns TPD CSDA prop delay relative to low going edge of CSCL 50 ns 1. Serial interface operates down to VBAT = 1.0V but with 100kHz clock speed and degraded parameters. 8 1-7 CSCL CSDA 8 9 8 1-7 8 9 8 1-7 8 9 Start Condition Address R/W ACK Data ACK Data ACK Stop Condition TS TSU TH TL THD TPD |
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