AS3421 datasheet(38/61 Pages) AMSCO

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AS3421 AS3422

Datasheet - R e g i s t e r D e s c r i p t i o n

Table 29. MICS_CNTR Register

Name

Base

Default

MICS_CNTR

2-wire serial

00h (OTP)

Offset: 16h

Microphone Supply Regsiter

Configures the low battery threshold value

Bit

Bit Name

Default

Access

Bit Description

LowBat

R/W

0: default LowBat value

1: 100mV increase of LowBat threshold

DEL_ ANC_MUX

R/W

0: default startup timing of AS3421/22

1: HP_MUX_OTP is set to OTP value 0.8s after device startup

Table 30. PWRUP_CNTR Register

Name

Base

Default

PWRUP_CNTR

2-wire serial

00h (OTP)

Offset: 17h

PowerUp Control Register

Configures chip start-up speed. This is a special register, writing needs to be enabled by writing 10b to

Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.

Bit

Bit Name

Default

Access

Bit Description

SEQ_LOCK

R/W

0: additional bits can be fused inside register 16h & 17h

1: OTP fusing for register 16h & 17h gets locked, no more changes can be

done.

6:2

FAST_START

<4:0>

0 0000

R/W

0h: ~900ms start-up time

0Eh: ~600ms start-up time

LIN_AGC_OFF

R/W

0: Line Input AGC enabled

1: Line Input AGC switched off

MIC_AGC_OFF

R/W

0:Microphone Input AGC enabled

1: Microphone Input AGC switched off

Table 31. ANC_L Register

Name

Base

Default

ANC_L

2-wire serial

80h (OTP)

Offset: 30h

Left OTP Microphone Input Register

Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by

writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents.

Bit

Bit Name

Default

Access

Bit Description

TEST_BIT_1

for testing purpose only

6:0

MICL_VOL_OTP

<6:0>

000 0000

R/W

Volume settings for left microphone input, adjustable in 127 steps of 0.375dB

00 0000: MUTE

00 0001: -11.25dB gain

00 0010: -10.875 dB gain

11 1110: 35.625dB gain

11 1111: 36 dB gain

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