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AS3421 AS3422

Datasheet - D e t a i l e d D e s c r i p t i o n

Figure 31. Random Read

Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer

from the master.

The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the

device-write address and the word address.

In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address

transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located

by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on

the bus.

Figure 32. Sequential Read

Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference to the

Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data

bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master

has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently.

Figure 33. Current Address Read

To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer.

The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte

transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can

be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master

sends a not-acknowledge following the last data byte and a subsequent STOP condition.

S

DW

A

WA

A

N

A

read register

WA++

data

Sr

DR

P

S

DW

A

WA

A

N

A

read register

WA++

data

Sr

DR

P

reg_data 2

A

read register

WA++

reg_data n

...

A

read register

WA++

S

N

A

read register

WA++

data

DR

P

reg_data 2

A

read register

WA++

reg_data n

...

A

read register

WA++