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ADS5292IPFPR 数据表(PDF) 27 Page - Texas Instruments |
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ADS5292IPFPR 数据表(HTML) 27 Page - Texas Instruments |
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27 / 67 page  POWER SUPPLY AVDD, LVDD RESET SEN t 1 t 2 t 3 ADS5292 www.ti.com SLAS788B – NOVEMBER 2011 – REVISED JULY 2012 RESET TIMING Typical values at 25°C, MIN and MAX values across the full temperature range TMIN = –40°C to TMAX = 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 Power-on delay Delay from power up of AVDD and LVDD to RESET pulse active 1 ms t2 Reset pulse duration Pulse duration of active RESET signal 50 ns t3 Register write delay Delay from RESET disable to CS active 100 ns NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET has to be tied permanently HIGH. Figure 45. Reset Timing Diagram Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Link(s) :ADS5292 |
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