ADS5292IPFPR datasheet(52/67 Pages) TI1

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INP

INM

15 Ω

Cbond

~ 0.5 pF

Csamp

2 pF

Sampling

capacitor

Sampling

switch

Sampling

switch

Ron

10 Ω

Ron

10 W

Csamp

2 pF

15 Ω

Cpar1

0.1 pF

Lpkg ~ 2 nH

Cbond

~ 0.5 pF

Resr

200 W

Resr

200 W

Sampling

capacitor

Ron

40 Ω

Lpkg~ 2 nH

Cpar 2

1.0 pF

Cpar 2

1.0 pF

Ron

25 W

Cpar 3

0.3 pF

Ron

100 W

Cpar3

0. 3 pF

Ron

25 W

Ron

100 W

Vcm

1 kW

ADS5292

SLAS788B – NOVEMBER 2011 – REVISED JULY 2012

www.ti.com

APPLICATION INFORMATION

THEORY OF OPERATION

The ADS5292 is an octal channel, 12-bit high-speed ADC with sample rate up to 80 MSPS that runs off a single

1.8 V supply. All eight channels of the ADS5292 simultaneously sample their analog inputs at the rising edge of

the input clock. The sampled signal is sequentially converted by a series of small resolution stages, with the

outputs combined in a digital correction logic block. At every clock, edge the sample propagates through the

pipeline resulting in a data latency of 11 clock cycles.

The 14 data bits of each channel are serialized and sent out in either 1-wire (one pair of LVDS pins are used) or

2-wire (two pairs of LVDS pins are used) mode, depending on the LVDS output rate. When the data is output in

the 2-wire mode, it can reduce the serial data rate of the outputs, especially at higher sampling rates. Hence, low

cost FPGAs can be used to capture 80 MSPS/12bit data. Alternately, at lower sample rates, the 12-bit data can

be output as a single data stream over one pair of LVDS pins (1-wire mode). The device outputs a bit clock at 7x

and frame clock at 1x times the sample frequency in the 12-bit mode.

This 12-bit ADC achieves 70 dBFS SNR at 80MSPS. Its output resolution can be configured as 14-bit and 10-bit

if necessary. 72 dBFS and 61 dBFS SNRs are achieved when the ADS5292’s output resolution is 12-bit and 10-

bit respectively.

ANALOG INPUT

The analog inputs consist of a switched-capacitor based, differential sample and hold architecture. This

differential topology results in very good AC performance even for high input frequencies at high sampling rates.

The INP and INM pins are internally biased around a common-mode voltage of Vcm (0.95 V). For a full-scale

differential input, each input pin (INP and INM) must swing symmetrically between Vcm + 0.5V and Vcm - 0.5V,

resulting in a 2 VPP differential input swing. Figure 56 illustrates the equivalent circuit of the input sampling circuit.

Figure 56. Analog Input Circuit Model

DRIVE CIRCUIT

For optimum performance, the analog inputs must be driven differentially. This improves the common-mode

noise immunity and even order harmonic rejection. A 5

Ω to 15 Ω resistor in series with each input pin is

recommended to damp out ringing caused by package parasitic.

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