ADS5292IPFPR datasheet(10/67 Pages) TI1

10 / 67 page

ADS5292

SLAS788B – NOVEMBER 2011 – REVISED JULY 2012

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TIMING REQUIREMENTS

(1) (2) (3)

Typical values are at 25°C, AVDD = 1.8 V, LVDD = 1.8 V, sampling frequency = 80 MSPS, 12-bit, sine-wave input clock =

1.5-Vpp clock amplitude, CLOAD = 5 pF, RLOAD = 100 Ω, unless otherwise noted. MIN and MAX values are across the full

temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, LVDD = 1.7 V to 1.9 V.

PARAMETERS

CONDITIONS

MIN

TYP

MAX

UNITS

The delay in time between the rising edge of the input

Aperture delay

sampling clock and the actual time at which the sampling

occurs

Aperture delay variation

Across channels within the same device

±175

Across devices at same temperature and LVDD supply

2.5

voltage

Aperture jitter RMS

320

fs rms

Data latency

1-wire LVDS output interface

Clock cycles

2-wire LVDS output interface

Clock cycles

tSU

Data setup time

80 MSPS, 2 wire LVDS, 6x serialization

0.25

0.63

Data hold time

80 MSPS, 2 wire LVDS, 6x serialization

0.65

Input clock rising edge(zero cross) to frame clock rising

See Table 1 and

Clock propagation delay

edge(zero cross)

Table 2

tPROG

Variation of tPROG

Between two devices under the same conditions

±0.75

LVDS bit clock duty cycle

50%

Bit clock cycle-to-cycle jitter

ps rms

Frame clock cycle-to-cycle

ps rms

jitter

tRISE

Data rise time

Rise time is from -100mV to +100mV

0.2

tFALL

Data fall time

Fall time is from +100mV to -100mV

0.2

tCLKRISE

Output clock rise time

Rise time is from -100mV to +100mV

0.18

tCLKFALL

Output clock fall time

Fall time is from +100mV to -100mV

0.16

Time to valid data after coming out of COMPLETE

tWAKE

Wake-up Time

100

µs

POWER-DOWN mode

Time to valid data after coming out of PARTIAL POWER-

DOWN mode (with clock continuing to run during power-

µs

down)

(1)

Timing parameters are ensured by design and characterization and not tested in production.

(2)

Measurements are done with a transmission line of 100-

Ω characteristic impedance between the device and the load. Setup and hold

time specifications take into account the effect of jitter on the output data and clock.

(3)

Data valid refers to logic HIGH of 100 mV and logic LOW of –100 mV.

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