ADS5292IPFPR datasheet(29/67 Pages) TI1

29 / 67 page

ADS5292

www.ti.com

SLAS788B – NOVEMBER 2011 – REVISED JULY 2012

DEFAULT STATES AFTER RESET

•

Device is in normal operation mode with 12-bit ADC enabled for all channels.

•

Output interface is 1-wire, 12× serialization with 6×bit clock and 1×frame clock frequency

•

Serial readout is disabled

•

PDN pin is configured as global power-down pin

•

Digital gain is set to 0 dB.

•

Digital modes such as LFNS, digital filters, and so on, are disabled.

Table 3. Summary of Functions Supported by Serial Interface (1)(2)(3)(4)

ADDR.

D15

D14

D13

D12

D11

D10

NAME

DESCRIPTION

(HEX)

1: Self-clearing software RESET; . After reset, this bit is set to 0

RST

0: Normal operation.

EN_READOUT

1: READOUT of registers mode;0: Normal operation

0 – Disable access to register at address 0xF0

EN_HIGH_ADDRS

1 – Enable access to register at address 0xF0

1:Enable SYNC feature to synchronize the test patterns;

0: SYNC feature is disabled for the test patterns.

EN_SYNC

Note: this bit needs to be set as 1 when software or hardware test

pattern SYNC feature is used. see Reg.0x25[8] and 0x25[15].

RAMP_PAT_RESET_VAL

Ramp pattern reset value

1:Channel-specific ADC power-down mode;

PDN_CH<8:1>

0: Normal operation

1:Partial power-down mode - fast recovery from power-down;

PDN_PARTIAL

0: Normal operation

1:Register mode for complete power-down - slower recovery;

PDN_COMPLETE

0: Normal operation

1:Configures PD pin for partial power-down mode;

PDN_PIN_CFG

0:Configures PD pin for complete power-down mode

1: Channel-specific low frequency noise suppression mode enable;

LFNS_CH<8:1>

0: LFNS disabled

1: Enables output frame clock to be programmed through a pattern;

EN_FRAME_PAT

0: Normal operation on frame clock

ADCLKOUT<13:0>

14-bit pattern for frame clock on ADCLKP/ADCLKN pins

PRBS_SEED<15:0>

PRBS pattern starting seed value lower 16 bits

1: Swaps the polarity of the analog input pins electrically;

INVERT_CH<8:1>

0: Normal configuration

PRBS_SEED<22:16>

PRBS seed starting value upper 7 bits

(1)

The unused bits in each register (identified as blank table cells) must be programmed as '0'.

(2)

X = Register bit referenced by the corresponding name and description

(3)

Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.

(4)

Multiple functions in a register can be programmed in a single write operation.

Submit Documentation Feedback

Product Folder Link(s) :ADS5292

ADS5292IPFPR 数据表(PDF) 29 Page - Texas Instruments

ADS5292IPFPR 数据表(HTML) 29 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载

链接网址

ADS5292IPFPR 数据表(PDF) 29 Page - Texas Instruments

ADS5292IPFPR 数据表(HTML) 29 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表 下载

链接网址

数据表下载