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ADS5292IPFPR 数据表(PDF) 53 Page - Texas Instruments

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部件名 ADS5292IPFPR
功能描述  Octal Channel 12-Bit, 80 MSPS and Low-Power ADC
PDF  67 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

ADS5292IPFPR 数据表(HTML) 53 Page - Texas Instruments

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CLKP
5 kΩ
VCM
5 kΩ
6 pF
5 Ω
5 Ω
Lpkg
~ 2 nH
Cbond
~ 0.5 pF
Lpkg
~ 2 nH
Cbond
~ 0.5 pF
Resr
~ 200 Ω
Resr
~ 200 Ω
CLKM
Clock buffer
Ceq
Ceq
6 pF
0.1 F
m
10 W
2 pF
10 W
0.1 F
m
Differential
Input
INP
INM
ADS259x
ADS5292
www.ti.com
SLAS788B – NOVEMBER 2011 – REVISED JULY 2012
The drive circuit shows an R-C filter across the analog input pins. The purpose of the filter is to absorb the
glitches caused by the opening and closing of the sampling capacitors.
Figure 57. Drive Circuit
Large and Small Signal Input Bandwidth
The small signal bandwidth of the analog input circuit is high, around 550 MHz. When using an amplifier to drive
the ADS5292, the total noise of the amplifier up to the small signal bandwidth must be considered. The large
signal bandwidth of the device depends on the amplitude of the input signal. The ADS5292 supports 2 VPP
amplitude for input signal frequency up to 80 MHz. For higher frequencies (80 MHz), the amplitude of the input
signal must be decreased proportionally. For example, at 160 MHz, the device supports a maximum of 1 VPP
signal.
INPUT CLOCK
The ADS5292 is configured by default to operate with a single-ended input clock – CLKP is driven by a CMOS
clock and CLKM is tied to GND. The device can automatically detect a single-ended or differential clock. If CLKM
is grounded, the device treats clock as a single-ended clock. Operating with a low-jitter differential clock usually
gives better SNR performance, especially at input frequencies greater than 30 MHz. Typical clock termination
structures are listed in Figure 58 and Figure 59.
Ceq is approximately 1 to 3 pF, equivalent input capacitance of clock buffer.
Figure 58. Equivalent Circut of the Input Clock Circuit
Copyright © 2011–2012, Texas Instruments Incorporated
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