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ADS5292IPFPR 数据表(PDF) 35 Page - Texas Instruments

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部件名 ADS5292IPFPR
功能描述  Octal Channel 12-Bit, 80 MSPS and Low-Power ADC
PDF  67 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

ADS5292IPFPR 数据表(HTML) 35 Page - Texas Instruments

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ADS5292
www.ti.com
SLAS788B – NOVEMBER 2011 – REVISED JULY 2012
DESCRIPTION OF SERIAL REGISTERS
POWER-DOWN MODES
ADDR.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
(HEX)
0F
X
X
X
X
X
X
X
X
PDN_CH<8:1>
X
PDN_PARTIAL
X
PDN_COMPLETE
X
PDN_PIN_CFG
Each of the 8 channels can be individually powered down. PDN_CH<N> controls the power-down mode for ADC
channel <N>. In addition to channel-specific power-down, the ADS5292 also has two global power-down modes:
1. The partial power-down mode. It partially powers down the chip; recovery from this mode is faster in 5 µs,
provided that the clock has been running for at least 50 µs before exiting this mode.
2. The complete power-down mode. It completely powers down the chip, and involves a much longer recovery
time 100 µs.
In addition to programming the chip in either of these two power-down modes (through either the PDN_PARTIAL
or PDN_COMPLETE bits), the PD pin itself can be configured as either a partial power-down pin or a complete
power-down pin control. For example, if PDN_PIN_CFG=0 (default), when the PD pin is high, the device enters
complete power-down mode. However, if PDN_PIN_CFG=1, when the PD pin is high, the device enters partial
power-down mode.
LOW FREQUENCY NOISE SUPPRESSION MODE
ADDR.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
(HEX)
14
X
X
X
X
X
X
X
X
LFNS_CH<8:1>
The low frequency noise suppression mode is specifically useful in applications where good noise performance is
desired in the frequency band of 0 to 1 MHz (around DC). Setting this mode shifts the low-frequency noise of the
ADS5292 to approximately Fs/2, thereby, moving the noise floor around DC to a much lower value.
LFNS_CH<8:1> enables this mode individually for each channel. See Figure 38 and Figure 39.
ANALOG INPUT INVERT
ADDR.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
(HEX)
24
X
X
X
X
X
X
X
X
INVERT_CH<8:1>
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
35
Product Folder Link(s) :ADS5292



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