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DAC5687MPZPEP 数据表(PDF) 2 Page - Texas Instruments |
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DAC5687MPZPEP 数据表(HTML) 2 Page - Texas Instruments |
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2 / 75 page ![]() www.ti.com DESCRIPTION (CONTINUED) 100-Pin HTQFP CLKVDD CLKGND LPF PLLGND PLLVDD PHSTR SLEEP DVDD DGND EXTIO EXTLO BIASJ IOUTA1 IOUTA2 IOUTB1 IOUTB2 IOGND IOVDD 1.2-V Reference SDIO SDO SDENB SCLK AVDD AGND CLK2 CLK2C CLK1 CLK1C PLLLOCK DA[15:0] DB[15:0] TXENABLE RESETB Internal Clock Generation and 2y−8y PLL Clock Multiplier 2y−8y fdata FIR1 FIR2 FIR3 FIR4 x2 x2 x2 x2 x2 x2 x: sin(x) x: sin(x) A Offset A gain 16-bit DAC SIF NCO B Offset B gain cos sin 16-bit DAC QFLAG DAC5687-EP SGLS333 – JUNE 2006 The DAC5687 includes several input options: single-port interleaved data, even and odd multiplexing at half rate, and an input FIFO with either external or internal clock to ease the input timing ambiguity when the DAC5687 is clocked at the DAC output sample rate. ORDERING INFORMATION TA PACKAGE DEVICE 100-pin HTQFP(1) (P&P) PowerPAD™ plastic quad flat pack –55°C to 125°C DAC5687MPZPEP (1) Thermal pad size: 6 mm × 6 mm These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM 2 Submit Documentation Feedback |
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