DAC5687MPZPEP datasheet(4/75 Pages) TI1

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DAC5687-EP

SGLS333 – JUNE 2006

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

1, 4, 7, 9, 12,

AGND

Analog ground return

17, 19, 22, 25

2, 3, 8, 10, 14,

AVDD

Analog supply voltage

16, 18, 23, 24

BIASJ

Full-scale output current bias

Clock 1. In PLL clock mode and dual clock modes, provides data input rate clock. In external clock

CLK1

mode, provides optional input data rate clock to FIFO latch. When the FIFO is disabled, CLK1 is

not used and can be left unconnected.

CLK1C

Complementary input of CLK1

Clock 2. External and dual clock-mode clock. In PLL mode, CLK2 is unused and can be left

CLK2

unconnected.

CLK2C

Complementary of CLK2. In PLL mode, CLK2C is unused and can be left unconnected.

CLKGND

58, 64

Ground return for internal clock buffer

CLKVDD

Internal clock buffer supply voltage

34–36, 39–43,

A-channel data bits 15–0. DA15 is most significant bit (MSB). DA0 is least significant bit (LSB).

DA[15..0]

48–55

Order can be reversed by register change.

71–78, 83–87,

B-channel data bits 15–0. DB15 is most significant bit (MSB). DB0 is least significant bit (LSB).

DB[0..15]

90–92

Order can be reversed by register change.

27, 38, 45, 57,

DGND

69, 81, 88, 93,

Digital ground return

26, 32, 37, 44,

DVDD

56, 68, 82, 89,

Digital supply voltage

100

Used as external reference input when internal reference is disabled (i.e., EXTLO connected to

EXTIO

I/O

AVDD). Used as internal reference output when EXTLO = AGND, requires a 0.1-µF decoupling

capacitor to AGND when used as reference output.

Internal/external reference select. Internal reference selected when tied to AGND, external

EXTLO

I/O

reference selected when tied to AVDD. Output only when ATEST is not zero (register 0x1B bits 7

to 3).

IOUTA1

A-channel DAC current output. Full scale when all input bits are set 1.

IOUTA2

A-channel DAC complementary current output. Full scale when all input bits are 0.

IOUTB1

B-channel DAC current output. Full scale when all input bits are set 1.

IOUTB2

B-channel DAC complementary current output. Full scale when all input bits are 0.

IOGND

47, 79

Digital I/O ground return

IOVDD

46, 80

Digital I/O supply voltage

LPF

PLL loop filter connection

Synchronization input signal that can be used to initialize the NCO, course mixer, internal clock

PHSTR

divider, and/or FIFO circuits

PLLGND

Ground return for internal PLL

PLLVDD

PLL supply voltage. When PLLVDD is 0 V, the PLL is disabled.

In PLL mode, provides PLL lock status bit or internal clock signal. PLL is locked to input clock

PLLLOCK

when high. In external clock mode, provides input rate clock.

When qflag register is 1, the QFLAG pin is used by the user during interleaved data input mode to

QFLAG

identify the B sample. High QFLAG indicates B sample. Must be repeated every B sample.

RESETB

Resets the chip when low. Internal pullup.

SCLK

Serial interface clock

SDENB

Active-low serial data enable (always an input to the DAC5687)

Bidirectional serial data in three-pin interface mode, input only in 4-pin interface mode. Three-pin

SDIO

I/O

mode is the default after chip reset.

Serial interface data, unidirectional data output, if SDIO is an input. SDO is 3-stated when the

SDO

3-pin interface mode is selected (register 0x08 bit 1).

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