DAC5687MPZPEP datasheet(49/75 Pages) TI1

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PHSTR

PLLLOCK

MUX

CLK1

CLK1C

{PLLVDD, inv_plllock, dual_clk}

clk_in

Clock

Genera-

tor

CLK2

CLK2C

clk_out

FIFO

phstr sync to coarse mixer

PLL VCO

clk_cmix

Sequencer

Reset

sync_cm

D Q

Sequencer

Reset

PHSTR

clk_in

Only needs to be high for one clk_in period

clk_cmix

phstr at FIFO

Output

Sequencer

fs/2

clk_out

Input delay line + FIFO delay

Sequencer

fs/4

180

180 270

180

DAC5687-EP

SGLS333 – JUNE 2006

Figure 54. Logic Path for PHSTR Synchronization Signal to CMIX Reset

To enable the PHSTR synchronous reset, the serial interface bit sync_cm in register SYNC_CNTL must be set.

The coarse mixer sequence counter will be held reset when PHSTR is low and operates when PHSTR is high.

Figure 55. CMIX Reset Synchronization Timing

In addition to the reset function provided by the PHSTR signal, the phstr_del(1:0) bits in register ATEST allow

the user to select the initial (reset) state. Changing the cm_mode lower 2 bits produces the same phase shift

results.

Table 13. Initial State of CMIX After Reset

Fix Mix Selection

phstr_del(1:0)

Initial State at PHSTR

fS/2

00 and 10

Normal

fS/2

01 and 11

180 degree shift

fS/4

Normal

fS/4

90 degree shift

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