DAC5687MPZPEP datasheet(33/75 Pages) TI1

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Address: 0x1D, 0x1E, and 0x1F – Reserved

Serial Interface

DAC5687-EP

SGLS333 – JUNE 2006

Table 5.

atest(4:0)

PLLLOCK Output Signal

PLL Enabled (PLLVDD = 3.3 V)

PLL Disabled (PLLVDD = 0 V)

11101

fDAC

Normal operation

11110

fDAC divided by 2

Normal operation

11111

fDAC divided by 4

Normal operation

All others

Normal operation

phstr_del:

Adjusts the initial phase of the fs/2 and fs/4 blocks cmix block after PHSTR.

BIT 7

BIT 0

Factory Use Only

phstr_clkdiv_se

phstr_clkdiv_sel: Selects the clock used to latch the PHSTR input when restarting the internal dividers. When

set, the full DAC sample rate CLK2 signal latches PHSTR and when cleared, the divided down

input clock signal latches PHSTR.

Writes have no effect and reads will be 0x00.

The serial port of the DAC5687 is a flexible serial interface which communicates with industry standard

microprocessors and microcontrollers. The interface provides read/write access to all registers used to define

the operating modes of the DAC5687. It is compatible with most synchronous transfer formats and can be

configured as a 3- or 4-pin interface by sif4 in register config_msb. In both configurations, SCLK is the serial

interface input clock and SDENB is serial interface enable. For 3-pin configuration, SDIO is a bidirectional pin for

both data in and data out. For 4-pin configuration, SDIO is data in only and SDO is data out only.

Each read/write operation is framed by signal SDENB (serial data enable bar) asserted low for 2 to 5 bytes,

depending on the data length to be transferred (1 – 4 bytes). The first frame byte is the instruction cycle which

identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to

transfer the data. Table 6 indicates the function of each bit in the instruction cycle and is followed by a detailed

description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle.

Table 6. Instruction Byte of the Serial Interface

MSB

LSB

Bit

Description

R/W

Identifies the following data transfer cycle as a read or write operation. A high indicates a read

operation from the DAC5687 and a low indicates a write operation to the DAC5687.

[N1 : N0]

Identifies the number of data bytes to be transferred per Table 7. Data is transferred MSB first.

Table 7. Number of Transferred Bytes Within One

Communication Frame

Description

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

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