TNETX3110 datasheet(30/65 Pages) TI1

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TNETX3110

ThunderSWITCH

™ 8/3 ETHERNET™ SWITCH

WITH 8 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS047A – MARCH 1998 – REVISED APRIL 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 10. 10-Mbit/s Interface Connections

TNETX3110

TERMINAL

TNETE2008

TERMINAL

TH2CLK

←

IFCLK

TH2SYNC

←

IFSYNC

TH2COL

←

IFCOL

TH2CRS

←

IFCRS

TH2LINK

←

IFLINK

TH2RXD3

←

IFRXD3

TH2RXD2

←

IFRXD2

TH2RXD1

←

IFRXD1

TH2RXD0

←

IFRXD0

TH2RXDV

←

IFRXDV

TH2TXD3

→

IFTXD3

TH2TXD2

→

IFTXD2

TH2TXD1

→

IFTXD1

TH2TXD0

→

IFTXD0

TH2TXEN

→

IFTXEN

TH2RENEG

→

IFFORCEHD

The time multiplexing of this interface is shown in Figure 5. The interface runs synchronous to the

PHY-generated 20-MHz clock IFCLK. The MAC-to-PHY information for the first port in each group of eight (i.e.,

port 00, port 08, or port 16) is presented on the interface when the TH2SYNC terminal is high. The next clock

cycle that the interface carries is the information for the second port. This process continues for all eight ports,

each using the interface for one cycle. When all ports have been processed in this manner, the sequence

resumes with the first port and again when the TH2SYNC signal is asserted.

To improve latency-related issues, the PHY-to-MAC data are skewed by two slots, allowing the MAC to respond

to the input signals from the PHY in the same 400-ns cycle, rather than waiting for the next 400-ns cycle (which

would be the case if the signals were not skewed).

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