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TNETX3110 数据表(PDF) 53 Page - Texas Instruments

部件名 TNETX3110
功能描述  ThunderSWITCHE 8/3 ETHERNETE SWITCH WITH EIGHT 10-MBIT/S PORTS AND THREE 10-/100-MBIT/S PORTS
PDF  65 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETX3110 数据表(HTML) 53 Page - Texas Instruments

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TNETX3110
ThunderSWITCH
™ 8/3 ETHERNET™ SWITCH
WITH 8 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS047A – MARCH 1998 – REVISED APRIL 1999
53
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
THxCLK
(input)
THxSYNC
(input)
THxCOL
THxCRS
THxLINK
THxRXD3–THxRXD0
THxRXDV
(inputs)
THxTXEN
THxTXD3–THxTXD0
THxRENEG
(outputs)
1
2
2
5
3
6
4
8
7
Figure 12. 10-Mbit/s Interface (Ports 00–07)
10-/100-Mbit/s MAC interface
Figures 14 and 15 show the timings at 100 Mbit/s and 10 Mbit/s for the 10-/100-Mbit/s port interfaces to the
TNETE2101 devices.
10-/100-Mbit/s receive ports (08, 09, and 10)
timing requirements (see Note 7 and Figure 13)†
NO.
MIN
MAX
UNIT
1
tc(MxxRCLK)
Cycle time, MxxRCLK
25
25
ns
2
tw(MxxRCLKL)
Pulse duration, MxxRCLK low
ns
3
tw(MxxRCLKH)
Pulse duration, MxxRCLK high
14
ns
4
tsu(MxxRXD)
Setup time, MxxRXD3–MxxRXD0 valid before MxxRCLK
↑
5
ns
4
tsu(MxxRXDV)
Setup time, MxxRXDV valid before MxxRCLK
↑
5
ns
4
tsu(MxxRXER)
Setup time, MxxRXER valid before MxxRCLK
↑
5
ns
5
th(MxxRXD)
Hold time, MxxRXD3–MxxRXD0 valid after MxxRCLK
↑
5
ns
5
th(MxxRXDV)
Hold time, MxxRXDV valid after MxxRCLK
↑
5
ns
5
th(MxxRXER)
Hold time, MxxRXER valid after MxxRCLK
↑
5
ns
† xx = ports 08, 09, and 10
NOTE 7: Both MxxCRS and MxxCOL are driven asynchronously by the PHY. MxxRXD3–MxxRXD0 is driven by the PHY on the falling edge of
MxxRCLK. MxxRXD3–MxxRXD0 timing must be met during clock periods when MxxRXDV is asserted. MxxRXDV is asserted and
deasserted by the PHY on the falling edge of MxxRCLK. MxxRXER is driven by the PHY on the falling edge of MxxRCLK.
MxxRXD3–MxxRXD0
MxxRXDV
MxxRXER
(inputs)
MxxRCLK
(input)
4
5
1
2
2
Figure 13. 10-/100-Mbit/s Receive Ports



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