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TNETX3110 数据表(PDF) 9 Page - Texas Instruments |
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TNETX3110 数据表(HTML) 9 Page - Texas Instruments |
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9 / 65 page  TNETX3110 ThunderSWITCH ™ 8/3 ETHERNET™ SWITCH WITH 8 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS047A – MARCH 1998 – REVISED APRIL 1999 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) SDRAM interface TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION DA13 DA12 DA11 DA10 DA09 DA08 DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 212 210 209 207 206 205 204 203 202 200 199 198 196 195 O None SDRAM address bus (time-multiplexed bank, row, and column address). The address bus DA13–DA00 also provides the SDRAM mode register initialization value. DA13 is the most significant bit and DA00 is the least significant bit. DCAS 189 O None SDRAM column address strobe. DCAS, in conjunction with DRAS and DW, determines the SDRAM commands. DCLK 193 O None SDRAM clock (83.33-MHz clock to the SDRAMs). SDRAM commands, addresses, and data are sampled by the SDRAM on the rising edge of this clock. DD31 DD30 DD29 DD28 DD27 DD26 DD25 DD24 DD23 DD22 DD21 DD20 DD19 DD18 DD17 DD16 DD15 DD14 DD13 DD12 DD11 DD10 DD09 DD08 DD07 DD06 DD05 DD04 DD03 DD02 DD01 DD00 187 186 185 183 182 181 180 179 177 176 174 173 172 171 170 168 167 166 164 162 161 159 158 157 156 155 153 152 150 149 147 146 I/O Pullup SDRAM data bus (bidirectional bus used to carry SDRAM data). DD31–DD00 also output status information to indicate buffer operation type and port number. Internal pullup resistors are provided. DD31 is the most significant bit and the DD00 is the least significant bit. DRAS 190 O None SDRAM row address strobe. DRAS, with DCAS and DW, supplies the SDRAM commands. DW 191 O None SDRAM write select. DW, with DRAS and DCAS, supplies the SDRAM commands. |
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