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TNETX3110 数据表(PDF) 5 Page - Texas Instruments |
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TNETX3110 数据表(HTML) 5 Page - Texas Instruments |
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5 / 65 page  DA12–DA0 MRESET ECLK EDIO DD31–DD0 DCLK DRAS DCAS DW LEDDATA LEDCLK SDATA7–SDATA0 SAD1–SAD0 SRNW SCS SRDY DRAM Port LED Activity Port CPU Interface Serial MII Interface TRST TMS TCLK TDI TDO TAP Address Compare Statistics Storage MIB JTAG Test Access Port (TAP) EEPROM Port MxxTCLK MxxTXD3–MxxTXD0 MxxTXEN MxxTXER MxxCOL MxxCRS MxxRCLK MxxRXD3–MxxRXD0 MxxRXDV Three Ports (08–10)† 10/100 Mbit/s MxxRXER MxxFORCE10 MxxFORCEHD MxxLINK MDCLK MDIO Network Statistics Logic † xx is the port number that is being monitored. LED Interface TH2CLK TH2TXD3–TH2TXD0 TH2TXEN TH2COL TH2CRS TH2SYNC TH2RXD3–TH2RXD0 TH2RXDV TH2LINK TH2RENEG CPU Interface SDRAM Controller Controller (MAC) Controller (MAC) Controller (MAC) Controller (MAC) Controller (MAC) Controller (MAC) Controller (MAC) Controller (MAC) Controller (MAC) Controller (MAC) Controller (MAC) MII MII MII Eight Ports (00–07) 10 Mbit/s Queue Manager EEPROM Interface SDMA SINT STXRDY SRXRDY Miscellaneous Functions OSCIN RESET MII Figure 1. TNETX3110 Interface Block Diagram |
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