TNETX3110 datasheet(6/65 Pages) TI1

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TNETX3110

ThunderSWITCH

™ 8/3 ETHERNET™ SWITCH

WITH 8 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS047A – MARCH 1998 – REVISED APRIL 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

10-Mbit/s MAC multiplexed interface (ports 00–07)

TERMINAL

I/O

INTERNAL

DESCRIPTION

NAME

NO.

I/O

RESISTOR†

DESCRIPTION

TH2CLK

Pullup

Interface clock. Eight ports are supported on this interface and use this common 20-MHz

clock.

TH2COL

Pulldown

Interface collision sense. Assertion of TH2COL† during half-duplex operation indicates

network collision on the current port. Additionally, during full-duplex operation, transmission

of new frames does not start if this terminal is asserted.

TH2CRS

Pulldown

Interface carrier sense. TH2CRS indicates a frame carrier signal is being received on a

current port.

TH2LINK

Pulldown

Interface link presence. TH2LINK indicates the presence of the connection on a port.

– Low = no link

– High = link good

TH2RENEG

None

Interface renegotiate. A 1-0-1 sequence output on THxRENEG causes flow control and

half/full duplex for a port to be renegotiated with its companion physical-layer (PHY) device.

These THxRENEG terminals connect to IFFORCEHD on TNETE2008.

TH2RXD3

TH2RXD2

TH2RXD1

TH2RXD0

Pullup

Interface receive data. The receive data nibble from the current port is synchronous to

THxCLK. When the THxRXDV signal is 1, the receive data terminals contain valid information.

THxRXD0 is the least significant bit and THxRXD3 is the most significant bit. These signals

also are used to report the channel state to the MAC.

TH2TXEN

None

Interface transmit enable. TH2TXEN indicates valid transmit data on TH2TXD.

TH2SYNC

Pullup

Interface synchronize. TH2SYNC is used to synchronize the port traffic between the

media-access controller (MAC) and PHY. When TH2SYNC is a 1, the current MAC-to-PHY

path is the multiplexer interface TH0, and the PHY-to-MAC path is the multiplexer interface

TH2. TH2SYNC is sampled by the MAC on the falling edge of TH2CLK.

TH2TXD3

TH2TXD2

TH2TXD1

TH2TXD0

None

Interface transmit data. The transmit data nibble for the current port is synchronous to

TH2CLK. When TH2TXEN is asserted, these signals carry data. TH2TXD3–TH2TXD0 are

used during renegotiation to convey flow-control and duplex configuration requests to the

PHY. TH2TXD0 is the least significant bit and TH2TXD3 is the most significant bit.

TH2RXDV

Pulldown

Interface receive data valid. When TH2RXDV is a 1, it indicates that the TH2RXD lines contain

valid data.

† Internal resistors are provided to pull signals to known values. System designers should determine if additional pullups or pulldowns are required

in their system.

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