STM8S207MB datasheet(56/103 Pages) STMICROELECTRONICS

56 / 103 page

Electrical characteristics

STM8S207xx, STM8S208xx

56/103

Doc ID 14733 Rev 12

Figure 12.

fCPUmax versus VDD

10.3.1

VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the

VCAP pin. CEXT is specified in Table 18. Care should be taken to limit the series inductance

to less than 15 nH.

Figure 13.

External capacitor CEXT

Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.

Table 19.

Operating conditions at power-up/power-down

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tVDD

VDD rise time rate

2(1)

Guaranteed by design, not tested in production.

∞

µs/V

VDD fall time rate

2(1)

∞

tTEMP

Reset release

delay

VDD rising

1.7(1)

VIT+

Power-on reset

threshold

2.65

2.8

2.95

VIT-

Brown-out reset

threshold

2.58

2.73

2.88

VHYS(BOR)

Brown-out reset

hysteresis

fCPU [MHz]

SUPPLY VOLTAGE [V]

2.95

4.0

5.0

FUNCTIONALITY

GUARANTEED

@ TA -40 to 125 °C

NOT GUARANTEED

IN THIS AREA

5.5

FUNCTIONALITY GUARANTEED

@ TA -40 to 105 °C

Rleak

ESR

ESL

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