STM8S207MB datasheet(76/103 Pages) STMICROELECTRONICS

76 / 103 page

Electrical characteristics

STM8S207xx, STM8S208xx

76/103

Doc ID 14733 Rev 12

Figure 34.

Typical NRST pull-up resistance vs VDD @ 4 temperatures

Figure 35.

Typical NRST pull-up current vs VDD @ 4 temperatures

The reset network shown in Figure 36 protects the device against parasitic resets. The user

must ensure that the level on the NRST pin can go below the VIL max. level specified in

Table 41. Otherwise the reset is not taken into account internally. For power consumption

sensitive applications, the capacity of the external reset capacitor can be reduced to limit

charge/discharge current. If the NRSTsignal is used to reset the external circuitry, care must

be taken of the charge/discharge time of the external capacitor to fulfill the external device’s

reset timing conditions. The minimum recommended capacity is 10 nF.

Figure 36.

Recommended reset pin

protection

2.5

3.5

4.5

5.5

-40˚C

25˚C

85˚C

125˚C

VDD [V]

100

120

140

234

DD [V]

-40˚C

25˚C

85˚C

125˚C

ai15069

0.1µF

External

reset

circuit

STM8

Filter

RPU

VDD

Internal reset

NRST

(optional)

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