STM8S207MB datasheet(48/103 Pages) STMICROELECTRONICS

48 / 103 page

Option bytes

STM8S207xx, STM8S208xx

48/103

Doc ID 14733 Rev 12

OPT3

LSI_EN: Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on halt

0: No reset generated on halt if WWDG active

1: Reset generated on halt if WWDG active

OPT4

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL: Auto wakeup unit/clock

0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for for AWU

PRSC[1:0] AWU clock prescaler

00: 24 MHz to 128 kHz prescaler

01: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler

OPT5

HSECNT[7:0]: HSE crystal oscillator stabilization time

This configures the stabilisation time.

0x00: 2048 HSE cycles

0xB4: 128 HSE cycles

0xD2: 8 HSE cycles

0xE1: 0.5 HSE cycles

OPT6

Reserved

OPT7

WAITSTATE Wait state configuration

This option configures the number of wait states inserted when reading

from the Flash/data EEPROM memory.

1 wait state is required if fCPU > 16 MHz.

0: No wait state

1: 1 wait state

Table 13.

Option byte description (continued)

Option byte no.

Description

STM8S207MB 数据表(PDF) 48 Page - STMicroelectronics

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