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STM8S207MB 数据表(PDF) 36 Page - STMicroelectronics |
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STM8S207MB 数据表(HTML) 36 Page - STMicroelectronics |
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36 / 103 page  Memory and register map STM8S207xx, STM8S208xx 36/103 Doc ID 14733 Rev 12 Table 9. General hardware register map Address Block Register label Register name Reset status 0x00 5050 to 0x00 5059 Reserved area (10 bytes) 0x00 505A Flash FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF 0x00 505D FLASH _FPR Flash protection register 0x00 0x00 505E FLASH _NFPR Flash complementary protection register 0xFF 0x00 505F FLASH _IAPSR Flash in-application programming status register 0x00 0x00 5060 to 0x00 5061 Reserved area (2 bytes) 0x00 5062 Flash FLASH _PUKR Flash Program memory unprotection register 0x00 0x00 5063 Reserved area (1 byte) 0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00 0x00 5065 to 0x00 509F Reserved area (59 bytes) 0x00 50A0 ITC EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 0x00 50A2 to 0x00 50B2 Reserved area (17 bytes) 0x00 50B3 RST RST_SR Reset status register 0xXX(1) 0x00 50B4 to 0x00 50BF Reserved area (12 bytes) 0x00 50C0 CLK CLK_ICKR Internal clock control register 0x01 0x00 50C1 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area (1 byte) 0x00 50C3 CLK CLK_CMSR Clock master status register 0xE1 0x00 50C4 CLK_SWR Clock master switch register 0xE1 0x00 50C5 CLK_SWCR Clock switch control register 0xXX 0x00 50C6 CLK_CKDIVR Clock divider register 0x18 0x00 50C7 CLK_PCKENR1 Peripheral clock gating register 1 0xFF 0x00 50C8 CLK_CSSR Clock security system register 0x00 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF 0x00 50CB CLK_CANCCR CAN clock control register 0x00 |
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