| 数据搜索系统,热门电子元器件搜索 |
|
STA382BW 数据表(PDF) 53 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STA382BW 数据表(HTML) 53 Page - STMicroelectronics |
|
53 / 172 page ![]() STA382BW Register description: New Map Doc ID 022783 Rev 1 53/172 For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage. 2.0 channels, two full-bridges (OPER = 00) ● FFX1A -> OUT1A ● FFX1B -> OUT1B ● FFX2A -> OUT2A ● FFX2B -> OUT2B ● FFX3A -> OUT3A ● FFX3B -> OUT3B ● FFX4A -> OUT4A ● FFX4B -> OUT4B ● FFX1A/1B configured as ternary ● FFX2A/2B configured as ternary ● FFX3A/3B configured as line out ternary ● FFX4A/4B configured as line out ternary On channel 3 line out (LOC bits = 00, reg 0x17 bit D7, D6) the same data as channel 1 processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this configuration, neither volume control nor EQ has any effect on channels 3 and 4. In this configuration the PWM slot phase is the following as shown in Figure 21. Figure 21. 2.0 channels (OPER = 00) PWM slots OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |