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STA382BW 数据表(PDF) 89 Page - STMicroelectronics |
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STA382BW 数据表(HTML) 89 Page - STMicroelectronics |
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89 / 172 page  STA382BW Register description: New Map Doc ID 022783 Rev 1 89/172 Table 82. PLL register 0x54 bits Bit R/W RST Name Description 7R/W 0 PLL_DITH[1:0] “00”: PLL clock dithering disabled “01”: PLL clock dithering enabled (triangular) “10”: PLL clock dithering enabled (rectangular) “11”: reserved 6R/W 0 5R/W 0 PLL_NDIV PLL loop divider 4R/W 0 3R/W 0 2R/W 0 1R/W 0 0R/W 0 Table 83. PLL register 0x55 bits Bit R/W RST Name Description 7 R/W 0 PLL_DPD ‘0’: any PLL dividers change is implemented via PLL power-down ‘1’: PLL divider change will happen without PLL power- down 6 R/W 0 PLL_FCT ‘0’: PLL use integer ratio ‘1’: PLL use fractional ratio 5 R/W 0 PLL_STB PLL synchronous divider changes strobe 4 R/W 0 PLL_STBBYP ‘0’: PLL_STB is active ‘1’: PLL_STB control is bypassed 3R/W 0 PLL_IDIV[3:0] Input PLL divider 2R/W 0 1R/W 0 0R/W 0 Table 84. PLL register 0x56 bits Bit R/W RST Name Description 5 R/W 0 PLL_DIRP ‘0’: PLL configuration is determined by the MCS bits ‘1’: PLL configuration is determined by FRAC, IDIV and NDIV 4 R/W 0 PLL_PWD ‘0’: PLL normal behavior ‘1’: PLL is in power-down mode 3R/W 0PLL_BYP ‘0’: sys clock is from PLL ‘1’: sys clock is from external pin (PLL is bypassed) 2R/W 0 OSC_PD ‘0’: Normal behavior ‘1’: Internal oscillator is in power-down 0 R/W 0 BOOST32K ‘0’: Input oversampling selected by the IR bits ‘1’: Input oversampling is selected x3 |
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