 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
STA382BW 数据表(PDF) 88 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STA382BW 数据表(HTML) 88 Page - STMicroelectronics |
|
|
88 / 172 page  Register description: New Map STA382BW 88/172 Doc ID 022783 Rev 1 6.27 PLL configuration registers (address 0x52; 0x53; 0x54; 0x55; 0x56; 0x57) By default, the STA382BW is able to configure the embedded PLL automatically depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a manual PLL configuration can be used (setting PLL_DIRP to ‘1’) The output PLL frequency formula is: where Fin is the input clock frequency from the pad. D7 D6 D5 D4 D3 D2 D1 D0 PLL_FRAC[15:8] 00 00 00 0 0 D7 D6 D5 D4 D3 D2 D1 D0 PLL_FRAC[7:0] 00 00 00 0 0 D7 D6 D5 D4 D3 D2 D1 D0 PLL_DITH[1:0] PLL_NDIV[5:0] 00 00 00 0 0 D7 D6 D5 D4 D3 D2 D1 D0 PLL_DPD PLL_FCT PLL_STB PLL_STBBYP PLL_IDIV[3:0] 00 00 00 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved PLL_DIRP PLL_PWD PLL_BYP OSC_PD Reserved BOOST32K 00 00 00 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Reserved BYPSTATE PDSTATE OSCOK LOWCK NA NA NA NA NA NA NA NA Table 81. PLL factors PLL parameter Min Max FRAC 0 65535 IDIV 0 3 NDIV 5 55 Fin NDIV () IDIV 1 + () --------------------------- FRAC 65536 ----------------- ⎝⎠ ⎛⎞ + ⎝⎠ ⎛⎞ × |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
