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SPEAr1340

Timing characteristics

Doc ID 023063 Rev 4

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5.3.2

Cortex-A9 trace timing characteristics

This section describes the timing characteristics for the ARM trace which works on both

rising edge and falling edge of the ARM_TRCCLK clock.

The timing characterization is performed assuming an output load capacitance of 20 pF on

the outputs and using PLL1 as the clock source for the timing extractions.

Figure 18.

ARM trace timing waveform

Table 60.

JTAG timing characteristics

Symbol

Description

Min

Max

Unit

TCLK

ARM_TCK clock period

33.3

TCLKhigh ARM_TCK pulse high

–

TCLKlow ARM_TCK pulse low

–

ARM_TCK to ARM_TDO output delay

Tsdata

Setup time for ARM_TDI and ARM_TMS data

Thdata

Hold time for ARM_TDI and ARM_TMS data

Tsreset

Setup time for ARM_TRSTn reset

Threset

Hold time for ARM_TRSTn reset

Table 61.

ARM trace timing characteristics

Symbol

Description

Min

Max

Unit

TCLK

ARM_TRCCLK clock period

TCLKhigh ARM_TRCCLK pulse high

2.9

–

TCLKlow ARM_TRCCLK pulse low

2.9

–

TDrise

ARM_TRCCLK to ARM_TRCDATA0..ARM_TRCDATA31,

ARM_TRCCTL output delay

-3.7

TDfall

ARM_TRCCLK to ARM_TRCDATA0..ARM_TRCDATA31,

ARM_TRCCTL output delay

-4

3.7

ARM_TRCCLK

ARM_TRCDATA

ARM_TRCCTL

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