SPEAR1340 datasheet(154/200 Pages) STMICROELECTRONICS

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Timing characteristics

SPEAr1340

154/200

Doc ID 023063 Rev 4

5.4

CAM timing characteristics

This section describes the timing characteristics of the four camera input interfaces which

can work on the clock rising edge or on the clock falling edge.

The timing characterization is performed assuming an input transition of 2 ns on all the

inputs and CAMx_PIXCLK and using PLL1 as the clock source for the timing extractions.

Figure 19.

CAM timing waveform

x = 1..4.

Table 62.

CAMx timing characteristics

Symbol

Description

Min

Max

Unit

TCLK

CAMx_PIXCLK clock period

6.5

–

TCLKhigh

CAMx_PIXCLK pulse high

2.9

–

TCLKlow

CAMx_PIXCLK pulse low

2.9

–

CAM1

Tspos

Setup time for CAM1 data respect to clock rising edge

5.4

–

Thpos

Hold time for CAM1 data respect to clock rising edge

-0.7

–

Tsneg

Setup time for CAM1 data respect to clock falling edge

5.6

–

Thneg

Hold time for CAM1 data respect to clock falling edge

-0.8

–

CAM2

Tspos

Setup time for CAM2 data respect to clock rising edge

5.7

–

Thpos

Hold time for CAM2 data respect to clock rising edge

-0.3

–

Tsneg

Setup time for CAM2 data respect to clock falling edge

5.9

–

Thneg

Hold time for CAM2 data respect to clock falling edge

-0.4

–

Thpos

CAMx_PIXCLK

(input)

CAMx_DATA[0..7],

CAMx_VSYNC,

CAMx_HSYNC

(1)

(with polarity configured as

rising edge)

TCLKhigh

TCLKlow

Tspos

CAMx_DATA[0..7],

CAMx_VSYNC,

CAMx_HSYNC

(1)

(with polarity configured as

falling edge)

Thneg

Tsneg

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