SPEAR1340 datasheet(168/200 Pages) STMICROELECTRONICS

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Timing characteristics

SPEAr1340

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Doc ID 023063 Rev 4

5.8

GPIO/XGPIO timing characteristics

For edge-sensitive signals, the interrupt line is sampled by flip flops clocked by PCLK for

GPIOs and HCLK for XGPIOs, the APB and AHB clocks, normally running at 83 MHz and

166 MHz respectively.

The minimum pulse width required for interrupt detection on signal edge is:

3*TPCLK (36 ns at 83 MHz) for GPIO

3*THCLK (18 ns at 166 MHz) for XGPIO

5.9

I2C timing characteristics

The timing of high and low level of SCL (TSCLHigh and TSCLLow) are programmable.

Figure 31.

I2C timing waveform

TCLKlow

MAC_MDC pulse width low

Setup time for MDIO input

Hold time for MDIO input

When MDIO is used as output, the data is launched on the falling edge of the clock as shown in Figure 30.

Table 78.

MAC_MDC/MAC_MDIO timing characteristics (continued)

Symbol

Description

Min

Max

Unit

I2Cx_SCL

I2Cx_SDA

tSCLHigh

tSU-STA

tHD-STA

tSU-DAT

tSU-STO

tHD-STO

tSCLLow

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