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SPEAR1340 数据表(PDF) 172 Page - STMicroelectronics

部件名 SPEAR1340
功能描述  Dual-core Cortex A9 HMI embedded MPU
PDF  200 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

SPEAR1340 数据表(HTML) 172 Page - STMicroelectronics

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Timing characteristics
SPEAr1340
172/200
Doc ID 023063 Rev 4
5.11
MCIF timing characteristics
5.11.1
Synchronous mode (SD/SDIO/MMC)
This section describes the timing characteristics for MCIF when interfacing SD/SDIO/MMC
synchronous memories.
The tables below show the timings for the high-speed and full-speed modes.
The timing characterization is performed assuming an output load capacitance of 10 pF on
all the outputs, an input transition of 2ns on all the inputs and using PLL1 as source of the
clock used for the timings extraction.
The MCI_ADDR_CLE_CLK signal is programmable via the MCIF registers. Refer to
RM0089, Reference manual, SPEAr1340 address map and registers
Figure 34.
MCIF - SD/SDIO/MMC mode timing waveform
1.
MCIF_OUT/MCIF_IN synchronous signals: MCIF_DATA0, MCIF_DATA[7..4], MCIF_DATAx_SD (x= 1..3),
MCIF_SD_CMD
Table 84.
MCIF - SD/SDIO High speed mode timing characteristics
Symbol
Description
Min
Max
Unit
tCLK
MCIF_ADDR1_CLE_CLK clock period
20
–
ns
tCLKhigh
MCIF_ADDR1_CLE_CLK pulse high
tCLK/2-1
–
ns
tCLKlow
MCIF_ADDR1_CLE_CLK pulse low
tCLK/2-1
–
ns
tD
MCIF_ADDR1_CLE_CLK to MCIF_OUT output delay
0.2
6.1
ns
ts
Setup time for MCIF_IN data
14
ns
th
Hold time for MCIF_IN data
1.3
ns
Table 85.
MCIF - SD/SDIO Full speed mode timing characteristics
Symbol
Description
Min
Max
Unit
tCLK
MCIF_ADDR1_CLE_CLK clock period
40
–
ns
tCLKhigh
MCIF_ADDR1_CLE_CLK pulse high
tCLK/2-1
–
ns
MCIF_ADDR1_CLE_CLK
(output)
MCIF_OUT (output)
(1)
MCIF_IN (input)
(1)
tCLKhigh
tCLKlow
th
tsu
td



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