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SPEAR1340 数据表(PDF) 188 Page - STMicroelectronics |
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SPEAR1340 数据表(HTML) 188 Page - STMicroelectronics |
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188 / 200 page  Timing characteristics SPEAr1340 188/200 Doc ID 023063 Rev 4 5.17 VIP timing characteristics This section describes the timing characteristics of the video input parallel block. The timing characterization is performed assuming an input transition of 2 ns on all the inputs and using VIP_PIXCLK as source of the clock for the timings extraction. Figure 50. VIP timing waveform Table 105. VIP timing characteristics Symbol Description Min Max Unit TCLK VIP_PIXCLK clock period 6.5 – ns TCLKhigh VIP_PIXCLK pulse high 2.9 – ns TCLKlow VIP_PIXCLK pulse low 2.9 – ns Ts Setup time for VIP data 6 ns Th Hold time for VIP data -0.71 ns Th VIP_PIXCLK (input) VIP_R[0..15], VIP_G[0..15], VIP_B[0..15], VIP_VSYNC, VIP_DE TCLKhigh TCLKlow Ts |
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