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M24LR64E-R 数据表(PDF) 53 Page - STMicroelectronics

部件名 M24LR64E-R
功能描述  64-Kbit EEPROM with password protection, dual interface & energy harvesting: 400 kHz I²C bus & ISO 15693 RF protocol at 13.56 MHz
PDF  140 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M24LR64E-R 数据表(HTML) 53 Page - STMicroelectronics

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M24LR64E-R
Bit representation and coding
Doc ID 022712 Rev 3
53/140
11
Bit representation and coding
Data bits are encoded using Manchester coding, according to the following schemes. For
the low data rate, same subcarrier frequency or frequencies is/are used. In this case, the
number of pulses is multiplied by 4 and all times increase by this factor. For the Fast
commands using one subcarrier, all pulse numbers and times are divided by 2.
11.1
Bit coding using one subcarrier
11.1.1
High data rate
A logic 0 starts with eight pulses at 423.75 kHz (fC/32) followed by an unmodulated time of
18.88 µs, as shown in Figure 23.
Figure 23.
Logic 0, high data rate
For the fast commands, a logic 0 starts with four pulses at 423.75 kHz (fC/32) followed by an
unmodulated time of 9.44 µs, as shown in Figure 24.
Figure 24.
Logic 0, high data rate, fast commands
A logic 1 starts with an unmodulated time of 18.88 µs followed by eight pulses at 423.75 kHz
(fC/32), as shown in Figure 25.
Figure 25.
Logic 1, high data rate
For the Fast commands, a logic 1 starts with an unmodulated time of 9.44 µs followed by
four pulses of 423.75 kHz (fC/32), as shown in Figure 26.
Figure 26.
Logic 1, high data rate, fast commands
37.76µs
ai12076
18.88µs
ai12066
37.76µs
ai12077
18.88µs
ai12067



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