M24LR64E-R datasheet(62/140 Pages) STMICROELECTRONICS

部件名	M24LR64E-R

功能描述	64-Kbit EEPROM with password protection, dual interface & energy harvesting: 400 kHz I²C bus & ISO 15693 RF protocol at 13.56 MHz

PDF	140 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

62 / 140 page

Data storage format identifier (DSFID)

M24LR64E-R

62/140

Doc ID 022712 Rev 3

Data storage format identifier (DSFID)

The data storage format identifier indicates how the data is structured in the M24LR64E-R

memory. The logical organization of data can be known instantly using the DSFID. It can be

programmed and locked using the Write DSFID and Lock DSFID commands.

15.1

CRC

The CRC used in the M24LR64E-R is calculated as per the definition in ISO/IEC 13239. The

initial register contents are all ones: “FFFF”.

The two-byte CRC is appended to each request and response, within each frame, before

the EOF. The CRC is calculated on all the bytes after the SOF up to the CRC field.

Upon reception of a request from the VCD, the M24LR64E-R verifies that the CRC value is

valid. If it is invalid, the M24LR64E-R discards the frame and does not answer the VCD.

Upon reception of a response from the M24LR64E-R, it is recommended that the VCD

verifies whether the CRC value is valid. If it is invalid, actions to be performed are left to the

discretion of the VCD designer.

The CRC is transmitted least significant byte first. Each byte is transmitted least significant

bit first.

Table 22.

CRC transmission rules

LSByte

LSBit MSBit

MSByte

LSBit MSBit

CRC 16 (8 bits)

M24LR64E-R 数据表(PDF) 62 Page - STMicroelectronics