M24LR64E-R datasheet(33/140 Pages) STMICROELECTRONICS

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M24LR64E-R

I2C device operation

Doc ID 022712 Rev 3

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5.5.1

I²C timeout on Start condition

I²C communication with the M24LR64E-R starts with a valid Start condition, followed by a

device select code.

If the delay between the Start condition and the following rising edge of the Serial Clock

(SCL) that samples the most significant of the Device Select exceeds the tSTART_OUT time

(see Table 123), the I²C logic block is reset and further incoming data transfer is ignored

until the next valid Start condition.

Figure 7.

I²C timeout on Start condition

5.5.2

I²C timeout on clock period

During data transfer on the I²C bus, if the serial clock pulse width high (tCHCL) or serial clock

pulse width low (tCLCH) exceeds the maximum value specified in Table 123, the I²C logic

block is reset and any further incoming data transfer is ignored until the next valid Start

condition.

5.6

Memory addressing

To start a communication between the bus master and the slave device, the bus master

must initiate a Start condition. Following this, the bus master sends the device select code,

shown in Table 2 (on Serial Data (SDA), the most significant bit first).

The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable

“Address” (E2,1,1). To address the memory array, the 4-bit device type identifier is 1010b.

Refer to Table 2.

The eighth bit is the Read/Write bit (RW). It is set to 1 for Read and to 0 for Write operations.

If a match occurs on the device select code, the corresponding device gives an

acknowledgment on serial data (SDA) during the ninth bit time. If the device does not match

the device select code, it deselects itself from the bus, and goes into Standby mode.

MS19779V1

SCL

SDA

tSTART_OUT

Start

condition

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