M24LR64E-R datasheet(34/140 Pages) STMICROELECTRONICS

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I2C device operation

M24LR64E-R

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Doc ID 022712 Rev 3

Figure 8.

Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited)

5.7

Write operations

Following a Start condition, the bus master sends a device select code with the Read/Write

bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two

address bytes. The device responds to each address byte with an acknowledge bit, and

then waits for the data byte.

Writing to the memory may be inhibited if the I2C_Write_Lock bit = 1. A Write instruction

issued with the I2C_Write_Lock bit = 1 and with no I2C_Password presented does not

modify the memory contents, and the accompanying data bytes are not acknowledged, as

shown in Figure 8.

Each data byte in the memory has a 16-bit (two-byte wide) address. The most significant

byte (Table 3) is sent first, followed by the least significant byte (Table 4). Bits b15 to b0 form

the address of the byte in memory.

Table 18.

Operating modes

Mode

RW bit

Bytes

Initial sequence

Current address read

Start, device select, RW = 1

Random address read

Start, device select, RW = 0, address

reStart, device select, RW = 1

Sequential read

≥ 1

Similar to current or random address read

Byte write

Start, device select, RW = 0

Page write

≤ 4 bytes

Start, device select, RW = 0

Byte Write

Dev select

Byte address

Data in

Page Write

Dev select

Byte address

Data in 1

Data in 2

AI15115

Page Write

(cont'd)

Data in N

ACK

NO ACK

R/W

ACK

NO ACK

R/W

NO ACK

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