M24LR64E-R datasheet(35/140 Pages) STMICROELECTRONICS

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M24LR64E-R

I2C device operation

Doc ID 022712 Rev 3

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When the bus master generates a Stop condition immediately after the Ack bit (in the tenth-

bit time slot), either at the end of a byte write or a page write, the internal write cycle is

triggered. A Stop condition at any other time slot does not trigger the internal write cycle.

After the Stop condition, the delay tW, and the successful completion of a Write operation,

the device’s internal address counter is incremented automatically, to point to the next byte

address after the last one that was modified.

During the internal write cycle, the serial data (SDA) signal is disabled internally, and the

device does not respond to any requests.

5.8

Byte write

After the device select code and the address bytes, the bus master sends one data byte. If

the addressed location is write-protected by the I2C_Write_Lock bit (= 1), the device replies

with NoAck, and the location is not modified. If the addressed location is not write-protected,

the device replies with Ack. The bus master terminates the transfer by generating a Stop

condition, as shown in Figure 9.

5.9

Page write

The Page write mode allows up to four bytes to be written in a single write cycle, provided

that they are all located in the same “row” in the memory: that is, the most significant

memory address bits (b12-b2) are the same. If more bytes are sent than fit up to the end of

the row, a condition known as “roll-over” occurs. This should be avoided, as data starts to

become overwritten in an implementation-dependent way.

The bus master sends from one to four bytes of data, each of which is acknowledged by the

device if the I2C_Write_Lock bit = 0 or the I2C_Password was correctly presented. If the

I2C_Write_Lock_bit = 1 and the I2C_password are not presented, the contents of the

addressed memory location are not modified, and each data byte is followed by a NoAck.

After each byte is transferred, the internal byte address counter (inside the page) is

incremented. The transfer is terminated by the bus master generating a Stop condition.

Figure 9.

Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled)

Byte Write

Dev Select

Byte address

Data in

Page Write

Dev Select

Byte address

Data in 1

Data in 2

AI15116

Data in N

ACK

R/W

ACK

R/W

ACK

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