ADP2441ACPZ-R2 datasheet(29/32 Pages) AD

29 / 32 page

Data Sheet

ADP2441

Rev. A | Page 29 of 32

POWER DISSIPATION AND THERMAL CONSIDERATIONS

POWER DISSIPATION

The efficiency of a dc-to-dc regulator is

100





OUT

Efficiency

(26)

where:

PIN is the input power.

POUT is the output power.

The power loss of a dc-to-dc regulator is

PLOSS = PIN − POUT

There are four main sources of power loss in a dc-to-dc regulator:



Inductor losses



Power switch conduction losses



Switching losses



Transition losses

Inductor Losses

Inductor conduction losses are caused by the flow of current

through the inductor DCR (internal resistance).

The inductor power loss (excluding core loss) is

PL = IOUT2 × DCRL

(27)

Power Switch Conduction Losses

Power switch conductive losses are due to the output current, IOUT,

flowing through the N-channel MOSFET power switches that

have internal resistance, RDS(ON). The amount of power loss can

be approximated as follows:

PCOND = [RDS(ON) –High Side × D + RDS(ON) – Low Side×(1 – D)] × IOUT2 (28)

Switching Losses

Switching losses are associated with the current drawn by the

driver to turn the power devices on and off at the switching

frequency. Each time a power device gate is turned on and off,

the driver transfers a charge (ΔQ) from the input supply to the

gate and then from the gate to ground.

The amount of switching loss can by calculated as follows:

PSW = QG_TOTAL × VIN × fSW

(29)

where:

QG_TOTAL is the total gate charge of both the high-side and low-

side devices and is approximately 28 nC.

fSW is the switching frequency.

Transition Losses

Transition losses occur because the N-channel MOSFET power

switch cannot turn on or off instantaneously. During a switch

node transition, the power switch provides all of the inductor

current, and the source-to-drain voltage of the power switch is

half the input, resulting in power loss. Transition losses increase

as the load current and input voltage increase, and these losses

occur twice for each switching cycle.

The transition losses can be calculated as follows:

OFF

OUT

TRANS

)

(







(30)

where tON and tOFF are the rise time and fall time of the switch

node and are each approximately 10 ns for a 24 V input.

THERMAL CONSIDERATIONS

The power dissipated by the regulator increases the die junction

temperature, TJ, above the ambient temperature, TA, as follows:

TJ = TA + TR

(31)

where the temperature rise, TR, is proportional to the power

dissipation, PD, in the package.

The proportionality coefficient is defined as the thermal

resistance from the junction temperature of the die to the

ambient temperature as follows:

TR = θJA + PD

(32)

where θJA is the junction-to-ambient thermal resistance and

equals 40°C/W for the JEDEC board (see Table 3).

When designing an application for a particular ambient tempera-

ture range, calculate the expected ADP2441 power dissipation (PD)

due to the conduction, switching, and transition losses using

Equation 28, Equation 29, and Equation 30, and then estimate

the temperature rise using Equation 31 and Equation 32. Improved

thermal performance can be achieved by implementing good

board layout. For example, on the ADP2441 evaluation board

(ADP2441-EVALZ), the measured θJA is <30°/W. Thermal perfor-

mance of the ADP2441 evaluation board is shown in the Figure 64

and Figure 65.

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