ADP2441ACPZ-R2 datasheet(21/32 Pages) AD

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Data Sheet

ADP2441

Rev. A | Page 21 of 32

30.0

24.6

19.2

13.8

8.40

3.00

510

DC BIAS VOLTAGE (V)

22µF/25V

10µF/25V

Figure 57. Capacitance vs. DC Bias Voltage

For example, to attain 20 μF of output capacitance with an output

voltage of 5 V while providing some margin for temperature

variation, use a 22 μF capacitor with a voltage rating of 25 V

and a 10 μF capacitor with a voltage rating of 25 V in parallel.

This configuration ensures that the output capacitance is

sufficient under all conditions and, therefore, that the device

exhibits stable behavior.

Table 10. Recommended Output Capacitors for ADP2441

Vendor

Capacitor

Murata

Taiyo Yuden

10 μF/25 V

GRM32DR71E106KA12L

TMK325B7106KN-TR

22 μF/25 V

GRM32ER71E226KE15L

TMK325B7226MM-TR

47 μF/6.3 V

GCM32ER70J476KE19L

JMK325B7476MM-TR

4.7 μF/50 V

GRM31CR71H475KA12L

UMK325B7475MMT

BOOST CAPACITOR

The boost pin (BST) is used to power up the internal driver for the

high-side power MOSFET. In the ADP2441, the high-side power

MOSFET is an N-channel device to achieve high efficiency in

mid and high duty cycle applications. To power up the high-side

driver, a capacitor is required between the BST and SW pins.

The size of this boost capacitor is critical because it affects the

light load functionality and efficiency of the device. Therefore,

choose a boost ceramic capacitor with a value between 10 nF to

22 nF with a voltage rating of 50 V and place the capacitor as

close as possible to the IC. It is recommended to use a boost

capacitor within this range because a capacitor beyond 22 nF

can cause the LDO to reach the current-limit threshold.

VCC CAPACITOR

The ADP2441 has an internal regulator to power up the internal

controller and the low-side driver. The VCC pin is the output of

the internal regulator. The internal regulator provides the pulse

current when the low-side driver turns on. Therefore, it is recom-

mended that a 1 μF ceramic capacitor be placed between the VCC

and PGND pins as close as possible to the IC and that a 1 μF

ceramic capacitor be placed between the VCC and AGND pins.

LOOP COMPENSATION

The ADP2441 uses peak current mode control architecture for

excellent load and line transient response. This control architecture

has two loops: an external voltage loop and an inner current loop.

The inner current loop senses the current in the low-side switch

and controls the duty cycle to maintain the average inductor

current. Slope compensation is added to the inner current loop

to ensure stable operation when the duty cycle is above 50%.

The external voltage loop senses the output voltage and adjusts

the duty cycle to regulate the output voltage to the desired

value. A transconductance amplifier with an external series RC

network connected to the COMP pin compensates the external

voltage loop.

ADP2441

VFB

COMP

AGND

RCOMP

CCOMP

0.6V

Figure 58. RC Compensation Network

LARGE SIGNAL ANALYSIS OF THE LOOP

COMPENSATION

The control loop can be broken down into the following three

sections:



VOUT to VCOMP



VCOMP to IL



IL to VOUT

PULSE-WIDTH

MODULATOR

VREF = 0.6V

INDUCTOR

CURRENT

SENSE

VOUT

VIN

VCOMP

CCOMP

COUT

RCOMP

RLOAD

ADP2441

Figure 59. Large Signal Model

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