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ADP2441ACPZ-R2 数据表(PDF) 20 Page - Analog Devices

部件名 ADP2441ACPZ-R2
功能描述  36 V,1 A, Synchronous, Step-Down DC-to-DC Regulator
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP2441ACPZ-R2 数据表(HTML) 20 Page - Analog Devices

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ADP2441
Data Sheet
Rev. A | Page 20 of 32
The inductor value is based on VIN(GEOMETRIC) as follows:
SW
GEOMETRIC
IN
OUT
GEOMETRIC
IN
OUT
IDEAL
f
V
V
V
V
L
)
(
)
(
)
(
3
.
3
Table 8. Inductor Values for Various VIN, VOUT, and fSW
Combinations
Inductor Value
fSW (kHz)
VIN (V)
VOUT (V)
Min (μH)
Max (μH)
300
12
3.3
22
27
300
12
5
27
33
300
24
3.3
27
33
300
24
5
39
47
300
24
12
56
68
300
36
3.3
27
33
300
36
5
39
47
300
36
12
68
82
600
12
3.3
12
15
600
12
5
15
18
600
24
3.3
15
18
600
24
5
18
22
600
24
12
27
33
600
36
3.3
15
18
600
36
5
22
27
1000
12
5
6.8
10
1000
24
5
10
12
1000
24
12
18
22
1000
36
5
12
15
To avoid inductor saturation and ensure proper operation, choose
the inductor value so that neither the saturation current nor
the maximum temperature rated current ratings are exceeded.
Inductor manufacturers specify both of these ratings in data
sheets, or the rating can be calculated as follows:
2
)
(
_
L
MAX
LOAD
PEAK
L
I
I
I
(10)
where:
ILOAD(MAX) is the maximum dc load current.
ΔIL is the peak-to-peak inductor ripple current.
Table 9. Recommended Inductors
Value (μH)
Small Size Inductors
(<10 mm × 10 mm)
Large Size Inductors
(>10 mm × 10 mm)
10
XAL4040-103ME
MSS1260
18
LPS6235-183ML
MSS1260
33
LPS6235-33ML
MSS1260
15
XAL4040-153ME
MSS1260
Output Capacitor Selection
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the regulator. The ADP2441 is
designed to operate with small ceramic output capacitors that
have low ESR and ESL; therefore, the device can easily meet
tight output voltage ripple specifications. For best performance,
use X5R or X7R dielectric capacitors with a voltage rating that is
1.5 times the output voltage and avoid using Y5V and Z5U
dielectric capacitors, which have poor temperature and dc bias
characteristics. Table 10 lists some recommended capacitor
from Murata and Taiyo Yuden.
For acceptable maximum output voltage ripple, determine the
minimum output capacitance, COUT(MIN), as follows:
)
(
8
1
MIN
OUT
SW
L
RIPPLE
C
f
ESR
I
V
(11)
Therefore,
)
(
8
)
(
ESR
I
V
f
I
C
L
RIPPLE
SW
L
MIN
OUT
(12)
where:
ΔVRIPPLE
is the allowable peak-to-peak output voltage ripple.
ΔIL
is the inductor ripple current.
ESR
is the equivalent series resistance of the capacitor.
fSW
is the switching frequency of the regulator.
If there is a step load requirement, choose the output capacitor
value based on the value of the step load. For the maximum accep-
table output voltage droop/overshoot caused by the step load,


DROOP
SW
STEP
OUT
MIN
OUT
V
f
I
C
3
)
(
)
(
(13)
where:
ΔIOUT(STEP) is the load step.
fSW is the switching frequency of the regulator.
ΔVDROOP is the maximum allowable output voltage droop/overshoot.
Select the largest output capacitance given by Equation 12 and
Equation 13. When choosing the type of ceramic capacitor for the
output filter of the regulator, select one with a nominal capacitance
that is 20% to 30% larger than the calculated value because the
effective capacitance degrades with dc voltage and temperature.
Figure 57 shows the capacitance loss due to the output voltage
dc bias for three X7R MLCC capacitors from Murata.



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